`include "define.svh"

module data_sram_like_interface(
    // from MEM-stage
    input wire                          data_sram_en,
    input wire [3 : 0]                  data_sram_wen,
    input wire [`REG_WIDTH - 1 : 0]     data_sram_addr,
    input wire [`REG_WIDTH - 1 : 0]     data_sram_wdata,
    // Master to slave outputs
    output reg                          data_req,
    output reg                          data_wr,
    output reg [1 : 0]                  data_size,
    output reg [`PC_WIDTH - 1 : 0]      data_addr,
    output reg [3 : 0]                  data_wstrb,
    output reg [`REG_WIDTH - 1 : 0]     data_wdata,
    // Slave to master inputs
    input wire                          data_addr_ok_i,
    input wire                          data_data_ok_i,
    // To IF/ID-stages
    output reg                          data_addr_ok_o,
    output reg                          data_data_ok_o
    // Data read send to MEM-stage directly
    );
    
    always_comb data_req = data_sram_en;
    always_comb data_wr = (|data_sram_wen);
    always_comb case (data_sram_wen)
        4'b0000, 4'b1111:                   data_size = 2'b10;
        4'b0001, 4'b0010, 4'b0100, 4'b1000: data_size = 2'b00;
        4'b0011, 4'b1100:                   data_size = 2'b01;
        default:                            data_size = 2'b00;
    endcase
    always_comb case (data_sram_wen)
        4'b0000, 4'b1111, 4'b0011, 4'b0001: data_addr = {data_sram_addr[31 : 2], 2'b00};
        4'b0010:                            data_addr = {data_sram_addr[31 : 2], 2'b01};
        4'b0100, 4'b1100:                   data_addr = {data_sram_addr[31 : 2], 2'b10};
        4'b1000:                            data_addr = {data_sram_addr[31 : 2], 2'b11};
        default:                            data_addr = `ZERO_REG;
    endcase
    always_comb data_wstrb = data_sram_wen;
    always_comb data_wdata = data_sram_wdata;
    always_comb data_addr_ok_o = data_addr_ok_i;
    always_comb data_data_ok_o = data_data_ok_i;
    
endmodule